The present invention relates to a phase-locked loop (PLL) circuit. A voltage control oscillator (VCO) constituting the PLL circuit is so controlled that the oscillation frequency matches an input signal as the reference. The VCO oscillates irrespective of whether a signal is input or not when power is turned ON or in the standby state in which a signal is not inputted. Accordingly, a long time is required from input of the input signal till the locked state is effected. Sometimes, the locked state is not achieved, even when an input signal comes in, due to characteristics of the VCO. It is an object of the present invention to overcome the defects as described above.
FIG. 10 is a block diagram that shows a general configuration of a PLL circuit. The PLL circuit comprises a phase/frequency comparator 11, a charge pump 12, a low-pass filter (LPF) 13, a voltage control oscillator (VCO) 14, and a frequency divider circuit 15. A reference signal a and a comparison signal b are inputted into the phase/frequency comparator 11. The phase/frequency comparator 11 compares the reference signal a with the comparison signal b in terms of phase and frequency. The phase/frequency comparator 11 outputs comparison difference signals c and d corresponding to the differences as the results of comparison. The charge pump 12 generates and outputs a pulse output e based on the comparison difference signals c and d outputted from the phase/frequency comparator 11.
The LPF 13 converts the pulse output e to an analog output voltage, and outputs the analog output voltage as control voltage f. The VCO 14 controls the oscillation frequency based on the control voltage f and outputs a frequency output signal g. The frequency divider circuit 15 outputs a signal obtained by dividing the frequency output signal g output by the VCO 14 as the comparison signal b to the phase/frequency comparator 11. Thus, in this PLL circuit, the phase/frequency comparator 11 always compares the reference signal a and the comparison signal b. A desired frequency output signal g is obtained by adjusting the control voltage f so that there is no difference between the two signals a and b.
The general processing sequence until the PLL circuit is locked is shown in FIG. 16 and FIG. 17. As shown in these figures, as the control voltage f is uncertain when power is turned ON or in the standby state where the reference signal a is not inputted, the control voltage f may sometimes rise up to the maximum level (power-supply voltage) or drop down to the minimum level (reference voltage). Therefore, since the oscillation frequency of the VCO 14 substantially deviates from the desired frequency, a long time is disadvantageously required before the locked state is effected.
The oscillation frequency of the VCO 14 generally rises in association with increase of the control voltage f. When the VCO 14 has reverse characteristics, that is, when the oscillation frequency drops in association with increase of the control voltage f at the upper or lower limit sides of the control voltage f, then, sometimes locking is not effected. In brief, as shown in FIG. 16, when the oscillation frequency of the VCO 14 drops in association with increase of the control voltage f in the upper limit side of the control voltage f, the control voltage f further increases in order to drop the oscillation frequency, and the control voltage f substantially deviates from that in the locked state. Similarly, the VCO 14 shows the same tendency in the lower limit side of the control voltage f, the control voltage f further decreases in order to raise the oscillation frequency, and in this case also the control voltage f substantially deviates from that in the locked state.
In order to overcome this problem, sometimes an adjustment circuit 16 is provided like in the PLL circuit shown in FIG. 11. As shown in FIG. 12, the adjustment circuit 16 comprises an inverter In1 into which a reset signal h is inputted as a reset signal, and a transistor Tr1 which turns ON in response to output from the inverter In1. When the reset signal h is inputted, the adjusting circuit 16 outputs a default voltage of prespecified amplitude to the LPF 13. This default voltage is outputted as the control voltage f from the LPF 13 to the VCO 14. Therefore, even if the VCO 14 operates with the tendency that the oscillation frequency drops in association with increase of the control voltage f, the control voltage f can be restored to a level close to that in the locked state by inputting the reset signal h.
In some other cases, a detection circuit 17 is provided like in the PLL circuit shown in FIG. 13 in order to shorten the time until the PLL circuit is locked. As shown in FIG. 14, the detection circuit 17 comprises a frequency comparator 18 and a charge pump 19. The frequency comparator 18 receives the reference signals a and the comparison signal b, and outputs the comparison difference signals m and n representing the difference between the earlier two signals. The charge pump 19 outputs a pulse output p based on the comparison difference signals m and n to the LPF 13. Thus, a voltage with prespecified amplitude is outputted as the control voltage f from the LPF 13 to the VCO 14. Therefore, the detection circuit 17 detects that a frequency difference between the reference signal a and comparison signal b is large and the control voltage f for the VCO 14 is adjusted in order to shorten the time required for locking.
FIG. 15 is a block diagram that shows a configuration of the frequency comparator 18 used in the detection circuit 17 shown in FIG. 14. The frequency comparator 18 comprises an edge detection circuit 181, a 90-degree delay circuit, six D flip flops FF1, FF2, FF3, FF4, FF5, FF6, an inverter In2, and four AND circuits An1, An2, An3, and An4.
However, the PLL circuit provided with the adjustment circuit 16 (see FIG. 11) can not be used at all in a circuit into which the reset signal h is not available. Therefore, the adaptability of such a PLL circuit to multi-purpose use is limited. Further, the logic of the frequency comparator 18 in the detection circuit 17 (see FIG. 13) is complicated. Therefore, circuit scale of the PLL circuit provided with the detection circuit 17 can not be small.
It is an object of the present invention to provide a PLL circuit which can be set in the locked state and also which normally operates even if a VCO used therein has the reverse characteristics.
In order to achieve the object described above, is a monitoring circuit provided in the PLL circuit according to the present invention. This monitoring circuit sets an effective range for a control voltage and monitors the control voltage. When the control voltage goes out of the effective range, the monitoring circuit sends a monitor signal to charge pump. Upon input of the monitor signal, the charge pump outputs a fixed voltage to the LPF. Thus, the VCO 24 is prevented from operating in the reverse characteristics area. Further, the VCO 24 oscillates in a prespecified frequency range in the state in which a reference signal is not inputted. As a consequence, the time required after a reference signal is inputted and until the locked state is effected is shortened.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.